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Share: 各种晶体管照片(Intel、TSMC&Samsung)from Chipworks  

2014-01-27 16:43:34|  分类: IC design |  标签: |举报 |字号 订阅

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Intel Transistors:

http://www.chipworks.com/en/technical-competitive-analysis/resources/blog/plenty-of-room-at-the-bottom-intel-thinks-so/

Contributed by: St.J. Dixon-Warren


Sub-100 nm Intel Technology

Chipworks has reverse engineered virtually every generation of Intel technology going back to before 1- ?m technology.  During our analysis of Intel’s 45 nm high k metal gate process, my colleague Ray Fontaine posted a review of the Intel reverse engineering results going back to 1992 on the Chipworks blog.

In 2001 we analyzed Intel’s 130 nm process used for the Pentium III. This was the first Intel process to feature copper metal. The contacted gate pitch was 530 nm and the minimum observed metal 1 pitch was 470 nm.  The 70 nm minimum gate length transistors used cobalt silicided source/drain diffusions and cobalt silicided poly gates, with L-shaped sidewall spacers. These dimensions are all more than an order of magnitude larger than the minimum proposed by Feynman.

Intel 130 nm transistors

The 90 nm Intel Pentium 4 Prescott devices were analyzed by Chipworks in 2004.  The 90 nm node saw a number of significant innovations, including nickel silicided source/drains and poly gates, and the introduction of strained transistors using stressed nitride for NMOS and embedded SiGe in the PMOS source drains. The contacted gate pitch was 320 nm and the minimum gate length for the NMOS was 45 nm, corresponding to a shrink by a factor of 0.64 from the 130 nm node. This is slightly better than the 0.7 shrink required by Moore’s Law for doubling the density at each node.

Intel 90 nm PMOS transistors

Intel 90 nm NMOS transistors

Our analysis of the Intel 65 technology in 2006 found essentially a shrink of the dimensions but with no major changes in the materials or the basic technology, other than the use of a nitrided gate oxide.  The contacted gate pitch was 230 nm and the minimum observed gate length was 38 nm.  The contacted gate pitch was shrunk by a factor of 0.72, while the physical gate length was shrunk by only a factor of 0.84.  Achieving the larger shrink in the contacted gate pitch was achieved by shrinking the contacts and the contact to gate spacing by a greater amount.  These dimensions are, of course, very impressive, but they are still significantly larger than the minimum proposed by Feynman in his paper. And we might be slowing down on Moores law.

Intel 65 nm PMOS transistors

Intel 65 nm NMOS transistors

The Intel Xeon E5410 Penryn 45 nm technology, analyzed by Chipworks in 2007, was a major milestone in the development of advanced CMOS technology, since it represented the first commercial high k metal gate technology device.  Early MOSFET transistors were based on aluminum gates; however, polysilicon displaced aluminum in the early 1970’s, due to poly’s ability to form self-aligned gates and due to better matching of the work functions for NMOS and PMOS transistors resulting in lower threshold voltages. The polysilicon gate technology was first developed at Fairchild in 1968, and it became the industry standard for nearly forty years.

The MOS transistors in the Intel 45 nm process features hafnium-based high k (HK) gate dielectric plus complex gate metallurgy that provided a different work function for the NMOS and PMOS transistors. The gates were formed in a “gate last” process by using a sacrificial polysilicon gate which was deposited on top of the HK gate dielectric.  The polysilicon was removed after the transistor engineering was completed and the gates were backfilled with the gate metallurgy (MG). The PMOS used raised SiGe source/drain diffusions, while the NMOS used recessed source/drain diffusions.

The contacted gate pitch for the 45 nm technology was 160 nm, with a minimum observed gate length of 42 nm.  The minimum gate length was actually longer than found in the previous 65 nm generation.

Intel 45 nm PMOS transistors

Intel 45 nm NMOS transistors

Intel’s 32 nm high k metal gate (HKMG) process appeared in the market in 2009. Chipworks analysis of the Intel Core i5 devices found that Intel had significantly evolved the process.  The “gate last” polysilicon replacement process was still used to form the transistors; however, at 32 nm the hafnium-based HK dielectric was deposited after removal for the poly, instead of before deposition. The contacted gate pitch was shrunk by a factor 0.7 to 113 nm with a 30 nm minimum gate length.  Quite dramatic changes were implemented in the contacts, which were formed using very short tungsten stubs, followed by copper via 0s that connected to the copper metal 1.

Intel 32 nm PMOS transistors

Intel 32 nm NMOS transistors

The arrival this year in Chipworks’ lab of Intel 22 nm devices represented yet another major milestone in the development of CMOS technology.   The conventional planar MOS transistor geometry was replaced by a tri-gate geometry, where the transistor gate wraps over a vertical silicon fin structure.

Source: Intel

Planar MOSFET versus finFET Geometry

Chipworks’ Intel 22 nm analysis found the contacted gate pitch to have been reduced to 90 nm, corresponding to a shrink by a factor of 0.8.  The metal gates were broadly similar in structure to those seen at 32 nm, except that the TiAl metal fill was partly replaced by W. The tri-gate fin structure is thinner than the TEM samples, and hence is almost completely obscured by the transistor gate in the conventional contacted-gate cross-sectional direction.

Intel 22 nm PMOS transistors

Intel 22 nm NMOS transistors

The fins are more clearly seen by cross-sectioning in the perpendicular direction, which is across the fins parallel to the transistor gates.  The HKMG wraps up over the transistor fin, which is ~ 8 nm wide at the mid-point.

Intel 22 nm PMOS fin

Intel 22 nm NMOS fin

The scaling of Intel’s CMOS technology has continued to follow Moore’s Law for the past ten years, with the contacted gate pitch scaling as approximately 4X the technology node. Each node corresponds to a shrink by a factor of 0.7, which corresponds to a doubling of the density of transistors per unit area.  The gate length has been scaled more slowly, while the gate oxide for poly processes leveled out at ~1.5 nm.   Intel is apparentlygearing up to make 14 nm technology, and we can expect a contacted gate pitch of about 60 nm; however, scaling the contacted gate pitch may not require that they scale the dimensions of the transistor fins.

The transistor fins found in the Intel 22 nm devices have essentially the same physical width as the minimum feature size proposed by Feynman in his 1959 paper.  The minimum fin pitch in the Intel 22 nm process is 60 nm; however, one could argue that Intel should now be nearly capable of printing the entire contents of Encyclopedia Britannica on to a die that is the size of the head of a pin – in fact, they claim that > 100 million 22-nm transistors will fit.

Source: Intel

Feynman would almost certainly be impressed by this technical achievement, and he’d likely agree that there is no longer plenty of room at the bottom, at least for 2D planar microelectronic device layout. But his visionary paper isn’t done.  Feynman’s paper includes a discussion of the extraordinary information densities possible in 3D structures.  He points out “that all of the information that man has carefully accumulated in all the books in the world can be written in the form of a cube of material one two-hundredths of an inch wide;” however, even though the tri-gate structure is the first and simplest excursion into 3D devices, fabricating high density 3D devices continues to be essentially unfeasible.

This doesn’t appear to be slowing Intel down – their R&D pipeline is heading down to 5-nm devices, though what they will look like is still to be decided.  There’s a few more interesting years (or decades) to come in nanotechnology!

Source: Intel

____________________________________________________________________________





TSMC Transistors:

http://www.chipworks.com/en/technical-competitive-analysis/resources/blog/a-review-of-tsmc-28-nm-process-technology/

contributed by Dr. Sinjin Dixon-Warren


TSMC was founded in 1987 and is the world’s largest foundry with 2011 revenues reaching $14.5 billion. According to their web site their total manufacturing capacity in 2011 was 13.2 million eight-inch wafer equivalents. They presently offer the full range of CMOS technologies from >0.5 ?m down to 28 nm.

The 28 nm technology platform appeared in production in 2010 and is offered in four process variants, denoted HP, HPM, HPL and LP.  We have analyzed three of these process variants to date, namely HP, HPL and LP. The 28 nm generation was the first time TSMC used high-k metal gate (HKMG) transistors. The HP and HPL technologies feature HKMG transistors, while the LP uses conventional poly gates, with an ONO gate dielectric. TSMC claims that their 28 nm process technology entered production in 2010; however, production devices were not available for analysis until mid-2011.

source: TSMC

The early adopters of TSMC’s most advanced process technologies continue to include Xilinx and Altera, the two leading FPGA manufacturers. These companies make high value, relatively low volume devices, and thus can afford the relatively low yields seen in the early ramp of a new CMOS technology. It should be no surprise that often the first devices at a new technology node to hit our labs come from these vendors; and it has been thus since our analysis of the 130 nm Altera Stratix in 2002 and the 90 nm Altera Stratix II in 2004. Back then, the Altera Stratix feature cobalt silicided poly transistors with a 530 nm contacted gate pitch, while the transistors in the Stratix II had a 370 nm contacted gate pitch.

Altera Stratix II 90 nm Transistor - TEM

Altera Stratix II 90 nm Transistor - TEM

The Xilinx XC7K325T Kintex-7 was the first 28 nm TSMC technology seen by our labs. We published our Structural Analysis Report in July of 2011. The XC7K325T was built using TSMC’s HPL technology, and featured 11 layers of backend metallization. The HKMG transistors had the channel direction rotated to the <100> orientation to increase the performance of the PMOS transistors. Embedded SiGe was not used for the PMOS source/drains. The transistor metallurgy was quite similar to that seen for the Intel 32 nm technology, with a TiN metal gate for the PMOS and a TiAlN metal gate for the NMOS (see my previous blog entitled Plenty of room at the bottom?). Hafnium oxide based dielectric was used for the HK layer, over a 2.0 nm thick layer of silicon dioxide.  The transistors are formed by a poly gate replacement, “gate last” process, similar to that used by Intel. Essentially, poly transistors are formed and all the source/drain engineering is completed. The poly is then removed and is replaced with NMOS and PMOS metallization. The contacted gate pitch for the transistors in the XC7K325T is 120 nm. According to TSMCthe HPL process is optimised for high performance with low leakage.

Xilinx XC7K325T Kintex-7 TSMC 28 nm HPL - Plan View TEM

Xilinx XC7K325T Kintex-7 TSMC 28 nm HPL - Plan View TEM

The Altera 5SGXEA7K2F40C2ES Stratix V was the second 28 nm TSMC technology to be analyzed our labs. Our Process Review Report was published in October of 2011.  The Stratix V was fabricated with the 28 nm HP process, which features embedded SiGe in the source/drain regions of the PMOS transistors, and 12 layers of metal in the backend. The HKMG structure was essentially identical to that used in the HPL process, but with a thinner (1.2 nm) SiO2 layer, as befits an HP process. The contacted gate pitch for the 5SGXEA7K2F40C2ES transistors was 120 nm.  According to TSMC, the 28 nm HP process is targeted for higher speed and performance, and they claim a 45% speed improvement when compared to the 40 nm process, with the same leakage per gate.

Altera 5SGXEA7K2F40C2 Stratix V 28 nm HP PMOS - TEM

Altera 5SGXEA7K2F40C2 Stratix V 28 nm HP PMOS - TEM

The FPGA manufacturers do not make extensive use of high density SRAM in their chip designs. Here we look to AMD’s graphics division and nVidia – both early adopters of TSMC’s new process technologies. Their graphics processing chips incorporate large amounts of high density 6T-SRAM. We usually find that AMD/ATI or nVidia are the first chips to market using the full feature set of TSMC’s advanced technologies, including high density SRAM.

Earlier this year, we completed a limited analysis of the high density SRAM on the AMD RadeonTM HD 7970 215-0821060 graphics processor, which was fabricated with TSMC’s HP process. Our TEM analysis confirmed the 215-0821060 transistor structure was identical to that seen in the Altera Stratix V device, as would be expected since both are based on the TSMC 28 nm HP process. The 215-0821060 features a 0.16 ?m2 6T-SRAM with the transistors arranged in a uniaxial layout. By contrast the 90 nm ATI 215PADAKA12FG graphics processor extracted from ATI Radeon X1950 Pro Graphics Card had a SRAM cell that is over five times bigger, at 0.86 ?m2.

AMD 215-0821060 28 nm HP 6T-SRAM at Poly - Plan View SEM

AMD 215-0821060 28 nm HP 6T-SRAM at Poly - Plan View SEM

Earlier in 2012, we found an example of TSMC 28 nm LP process in the Qualcomm MSM8960 Snapdragon S4 system-on-chip. The 28 nm LP process features polysilicon gates with embedded SiGe being used to increase the PMOS performance. The low power (LP) process was apparently the first available to have completed all TSMC’s qualification tests. TSMC claims that the 28 nm LP process is the low cost and fast time to market choice, ideal for low standby power applications such as cellular baseband. The process apparently provides a 20 percent speed improvement over the 40 nm LP process at the same leakage per gate.

The minimum contacted gate pitch was 120 nm. The 28 nm LP process is essentially a shrink of TSMC’s 40 nm LP process (with the addition of the e-SiGe for PMOS), which was (notably) used to fabricate the NVIDIA Tegra T20-H-A2 application processor. The 40 nm LP process featured a 160 nm contacted gate pitch in the logic regions.

Qualcomm MSM8960 28 nm LP Snapdragon S3 Transistor Gate - TEM

Qualcomm MSM8960 28 nm LP Snapdragon S3 Transistor Gate - TEM

The fourth and final 28 nm process offered by TSMC is the HPM technology. This process is targeted at mobile applications and apparently will support both high performance transistors and low power transistors on the same die, thus enabling higher performance mobile devices, while continuing to improve power performance, which is critical in battery powered gadgets.  TSMC claims the technology can provide better speed than 28 nm HP while giving similar leakage power to 28 nm LP. The wide performance/leakage coverage apparently makes 28 nm HPM ideal for applications from networking, tablet, to mobile consumer products. The HPM process has not yet been seen in the market yet, but Chipworks expects to see an example of the technology soon in a mobile device from a leading manufacture sometime soon – possibly a future variant of the Apple A6.



Samsung Transistors:

http://www.chipworksllc.com/en/technical-competitive-analysis/resources/blog/samsung-28-nm-apple-a7/

Contributed by: Sinjin Dixon-Warren

The Apple A7 processor used inside the iPhone 5s represents an extraordinary piece of engineering. Some details, such as the die layout, were discussed in an earlier blog. The A7 is fabricated with Samsung’s 28 nm low power(LP) gate first, high-k metal gate (HKMG) process technology. The process features nine layers of copper metallization with low-k dielectrics, plus an additional top aluminum metal layer. This blog article will focus on the front end of line (FEOL) transistor structure used in the A7, with comparison to advanced technologies used by both Apple and other vendors. The A7 gate first transistor structure is based on the Common Platform Technology, which is an alliance of IBM, Samsung, and GLOBALFOUNDRIES.

Chipworks has analyzed several generations of the Samsung process used to fabricate the A-series processors used in the iPhone and other Apple products. The A4 processor, released in September 2010, used a Samsung 45 nm polysilicon transistor process technology with 180 nm contacted gate pitch. The NMOS and PMOS transistor structure was essentially identical, with the main observable differences being in the materials used for the polysilicon gate and source/drain silicides.

Apple A4 45 nm MOS Transistors

 

Apple moved to a 10 metal, 32 nm HKMG process when they launched the A5 processor in March 2011. The gate first transistors featured a 130 nm contacted gate pitch, with a SiGe channel for the PMOS transistors, and separate work function metals for the NMOS and PMOS transistors. The SiGe channel improves the PMOS hole mobility and serves as part of the transistor work function engineering. The A6 processor, launched in September 2012, was also built with the Samsung 32 nm HKMG process.

The A7 is Apple’s first 28 nm device. The process technology is broadly similar to that used at 32 nm, with an ~10% shrink of the contacted gate pitch to 120 nm. The PMOS and NMOS transistors are easily distinguished due to marked differences in the transistor structure.

The NMOS transistors feature an NMOS work function metal gate (MG) deposited onto the high-k (HK) gate dielectric, which is comprised of hafnium oxide deposited over a thin layer of silicon dioxide. The process is described as gate first since the silicided polysilicon gate is deposited after the HKMG gate stack has been formed.

Apple A7 28 nm NMOS Transistors

The main distinguishing features of the PMOS transistors are the presence of a SiGe channel beneath the PMOS gates and a separate PMOS work function metal deposited over the HK dielectric stack. The NMOS MG layer is present over the PMOS MG layer, indicating that the PMOS transistors were formed first in the process flow. This NMOS MG layer would have no effect on the electrical characteristics of the PMOS transistor, although it may serve as a barrier to protect the PMOS MG layer during the polysilicon deposition process step. There are minor differences in the shape of the sidewall spacer structure (SWS) for the PMOS as compared to the NMOS transistors, while both transistor types are sealed with the same contact etch stop layer (CESL).

 

Apple A7 28 nm PMOS Transistors

The requirement for two different metal gates, with different work functions, is one of the major challenges for HKMG process technology. It is quite easily achieved in polysilicon gate technology through doping of the gate polysilicon as N-type for the NMOS and P-type for the PMOS transistors. A review of work function engineering has recently been published. Variations on the gate first PMOS SiGe channel technology used for the A7 have been used by GLOBALFOUNDRIES in the AMD 32 nm devices, and by IBM in the Power 7+ processors.

By contrast, Intel and TSMC have avoided the use of SiGe in the PMOS channel region; they achieve the work function difference purely through engineering of the metal gates. Furthermore, Intel and TSMC used a gate replacement (gate last) process, where the transistor engineering is completed using conventional polysilicon gates. The polysilicon is then removed and replaced with the NMOS and PMOS HKMG gate stack. A discussion of TSMC 28 nm process technology, which comes in four flavors, can be found in a previous blog posting. A review of many generations of Intel technology can be found in another earlier blog posting.


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