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Share: The State of the Art in 3D IC Technologies by Max Maxfield  

2013-12-02 10:11:04|  分类: Reading notes |  标签: |举报 |字号 订阅

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The State of the Art in 3D IC Technologies





In my previous column on the topic of 3D ICs, we pondered what the world used to be like before the dawn of these little rascals, including the use of lots of small, individually-packaged dice, the advent of system-on-chip (SoC) devices, and the introduction of system-in-package (SiP) assemblies.

In this column, we will consider the various forms of 3D IC technology, starting with the simpler incarnations and culminating in today's start-of-the-art implementations.

Simple stacking technologies
When we start to talk about 3D (three dimensional) ICs, the first thing we have to ask ourselves is, "What exactly do we mean by 3D?" As we shall see, this is not as trivial a question as it may first appear, because "3D" may mean different things to different people. For example, one early form of 3D IC technology -- which is still in use to this day for certain applications -- is to take a group of dice that all perform an identical function (like memory chips, for example), to build them into a 3D stack, to run connecting wires down the sides, and to present the resulting assembly in the form of a system-in-package (SiP):

3D die stack with connecting wires running down the sides.
3D die stack with connecting wires running down the sides.

Although the diagram above gives the appearance of being tall, thin, and ungainly, it's important to remember that each of the silicon die will be ~0.7mm thick (this may be reduced to only ~0.2mm thick if a back grinding process is used to thin the wafer).

Another approach that is commonly used is to mount one die on the SiP substrate using flip-chip technology, and to then mount a second die on top of the first using wire-bond technology as shown below:

A simple form of 3D IC/SiP.
A simple form of 3D IC/SiP.

Now, both of the technologies discussed above are very clever, but they really aren't what I think of when someone says "3D" in the context of integrated circuits. For that, we have to move to the next level…

To Page 2 >



Traditional 2D ICs/SiPs
Now, this is where things can start to become a little tricky if we aren't careful, so let's take this part of our discussions step-by-step. In fact, let's begin by taking a step back and reminding ourselves that -- in the case of a traditional 2D IC/SiP -- the die or dice are mounted in the package in a single plane. The reason I say "dice" is that a traditional 2D implementation may contain multiple chips as shown below:

A traditional 2D IC/SiP.
A traditional 2D IC/SiP.

For the sake of simplicity, we are showing only two dice in the SiP, but -- of course -- there could be many more. Also, in this illustration we are assuming that the dice are mounted on the SiP substrate using flip-chip technology (wire-bond technology could also be used). In this case, the flip-chip solder bumps will be ~100μm in diameter.

Let's also assume that the SiP substrate is of the laminate variety. That is, a small, fine-line printed circuit board with copper tracks and copper vias containing a number of tracking layers. Although this form of SiP technology really is incredibly impressive, the tracks on the SiP substrate are orders of magnitude larger than the tracks on the silicon dice. This discrepancy in size impacts performance and power consumption. Also, the larger tracks on the SiP substrate lead to routing congestion that places limitations on the number of die-to-die connections that can be realized.

Active-on-passive 3D ICs/SiPs with TSVs
The next step up the complexity ladder is to place a silicon interposer between the SiP substrate and the dice. As shown in the illustration below, the silicon interposer has through-silicon vias (TSVs) connecting the metallization layers on its upper and lower surfaces:

Active-on-passive 3D IC/SiP using a silicon interposer and TSVs.
Active-on-passive 3D IC/SiP using a silicon interposer and TSVs.

Some people refer to this technology as "2.5D" on the basis that the silicon interposer is passive -- that is, the interposer does not carry active components like transistors. Having said this, it's also not uncommon to refer to this as "active-on-passive 3D IC/SiP" technology.

In this case, the dice are attached to the silicon interposer using micro-bumps, which are ~10μm in diameter. Meanwhile, the silicon interposer is attached to the SiP substrate using regular flip-chip bumps, which will be ~100μm in diameter. The tracks on the silicon interposer's topside and backside metal layers (there can be multiple metal layers in both cases) are created using the same processes as the tracks on the silicon chips.

Although the silicon interposer and the silicon dice in the image above appear to be a little chunky, you have to remember that this drawing is not to scale. In reality (as we discussed earlier in this column), the dice -- and the silicon interposer -- may be only ~0.2mm to ~0.7mm thick.

As one example of the use of this technology, the Xilinx Virtex-7 2000T device has four FPGA dice attached to a silicon interposer, which supports ~10,000 silicon-speed connections between adjacent dice.

The advantage of using active-on-passive 3D IC/SiP technology is that it's an incremental step from traditional 2D IC/SiP technology that offers tremendous increases in capacity and performance. There are also yield advantages, because it's easier to make a number of small dice as opposed to a single large one. The main disadvantage is that it's non-trivial to make all of this work. ("If it were easy, everyone would be doing it," as the old saying goes.)

To Page 3 >



Active-on-active 3D ICs/SiPs with TSVs
The next step up the technology ladder is active-on-active 3D IC/SiPs, which involve at least one die being mounted on the top of another die, with the lower die employing through-silicon vias (TSVs) to allow the upper die to communicate with the lower die and the SiP substrate as illustrated below:

A simple active-on-active 3D IC/SiP using TSVs.
A simple active-on-active 3D IC/SiP using TSVs.

So, for example, we could have a memory die attached to a logic die (or vice versa), or an analog/RF die attached to a digital logic die, or… just imagine your own scenario.

The previous image showed the simplest possible implementation using this technology. In the not-so-distant future, we may expect to see multiple dice stacked on top of each other using TSVs, and multiple groups of dice connected together using a silicon interposer, all presented as a single SiP assembly as illustrated below:

A more complex 3D IC/SiP assembly.
A more complex 3D IC/SiP assembly.

Now, I know that this drawing looks a bit like a New York skyline and you may think it's all rather clunky, but -- as we previously noted -- you have to remember that the individual dice and the silicon interposer are only ~0.2mm to ~0.7mm thick, so the entire assembly shown above would be much smaller than you might suppose.

So just how prevalent is this technology? Is it for real, or is it all pie in the sky? Well, according to a 2012 report from Yole Développement:

    Last year,* the market value of all the devices using TSV packaged in 3D in the 3DIC or 3D-WLCSP platforms (CMOS image sensors, Ambient light sensors, Power Amplifiers, RF and inertial MEMS) was worth $2.7B. It will represent 9% of the total semiconductor value by 2017, hitting almost $40B.

    *2011

In my next installment in this miniseries we will consider alternative approaches involving esoteric materials and monolithic 3D IC technologies.

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