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Share: Analog: back to the future, part one  

2012-06-17 19:26:54|  分类: IC design |  标签: |举报 |字号 订阅

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人工的DRC和LVS,有机会自己改变规则。IC业的海贼时代呀。。

Analog: back to the future, part one

Steve Taranovich, Senior Technical Editor- June 5, 2012


Examining history provides an eye-opening education into our predecessors’ successes and failures and may provide lessons on what to avoid and what to emulate in our lives. This fact holds true not only in daily life but also in analog-IC and analog-circuit design. Innovative developers and developments were the foundations that led to 21st-century analog products that we now use in design. This article delves into early precision-op-amp development from National Semiconductor, Texas Instruments, and Linear Technology. Future installments will focus on Burr-Brown, Analog Devices, Microchip, and Maxim and on pioneers in analog technology.

At A Glance

- National Semiconductor designers provide a snapshot of the challenges of IC design from 30 to 40 years ago and how those experiences brought about today’s ICs.

- Designers developed so-called kludge boxes to verify the performance of designs and sometimes later used them in production-test equipment.

- Designers used simulation tools for validation, but they had to first perform manual calculations, and breadboarding was standard practice until the mid-1980s.

- Bob Dobkin, Linear Technology’s co-founder, vice president of engineering, and chief technology officer, spent his early design days at National Semiconductor, where his creativity was evident in moving early op amps beyond the 1-MHz-bandwidth barrier.
Genesis of the op-amp IC

By experiencing and learning from their growing pains along the course of IC development, a few designers stand out. Several of these designers were originally with National Semiconductor but are now part of Texas Instruments, and they are guiding chip-design engineers along a new path of success for the next level of ICs that circuit designers so desperately need in today’s demanding market. According to Dennis Monticelli, TI fellow, the story of computers is also the story of IC development; you can’t separate them. His co-worker, Chief Technology Officer Erroll Dietz, remembers the early days of analog ICs as the “Wild West of electronics.” Using design rules that they made up as they went along, these designers worked from transistor-kit parts, used copper-clad breadboards with sockets as design tools, and employed discrete resistors and capacitors (Figure 1).

“Kit parts were transistors manufactured in the linear IC-fab lines bonded up in metal can packages,” says Mike Maida, a distinguished member of the technical staff at TI. “Design rules [used] spacing to adhere to in IC layouts—for example, base to isolation, emitter inside base, [and the like]. Designers sometimes figured out their own [design rules] for special situations, such as reduced voltages, although the fab engineers had to sign off on them. We had little mylar ‘rulers’ to measure spacings on the IC composite drawings.”

The designers performed simulations using Level 2 Spice, which used an enhanced Grove equation, the most common MOS equation in all simulators. HKJ Ihantola and JL Moll in 1964 developed the equation (Reference 1). A discontinuity in transconductance at the time made life difficult for designers. Designs operating at frequencies higher than a few megahertz were difficult to breadboard, for example. “Simulation is a late-’70s thing,” says Maida. “No one simulated linear ICs [then].”



“There was a large discontinuity in the Level 2 MOS model for the region between strong inversion and weak inversion,” says Don Archer, also a distinguished member of the technical staff at TI. “When operating in the quasi-subthreshold region, model discontinuity was a major problem for convergence, and, when we started, there was no modeling group. We measured kit parts and came up with our own model parameters.”

The designers also lacked the ability to capture schematics; they had to manually type the netlist, including emitter, base, and collector values, and manually generate a schematic to check the accuracy of those values. They then added the simulation-node numbers to the hand-drawn schematic. The lines in the netlist might read, for example, Q1 8 7 4 0 NPN1, which would mean that Q1 is device type NPN1, with a collector node of eight, a base node of seven, an emitter node of four, and a substrate node of zero. They had to type a similar line for every transistor, resistor, and capacitor.

“To look at waveforms, we had to use plot and print [commands] to specify nodes to be printed or plotted,” says Farhood Moraveji, technical director at TI. “For more complex circuits with hierarchy, we had to use [a subcircuit command]. Back-end tools didn’t exist or were primitive. DRCs [design-rule checks] and LVS [layout-versus-schematic] checks were not automatic, and peers used to perform independent, manual LVS checks to verify that the circuit and the layout matched.”

Layout tools included a “beer check,” during which the designers placed circuit plots onto a light table. “You would invite your peers to the beer check for your IC layout,” says Archer. “You would buy them a beer for every mistake they found. We later got a more staid design manager, who insisted we call them layout checks instead of beer checks.”


According to Maida, the company also used color keys to compare one layer with another (Figure 2). The color keys were printed on Mylar sheets representing one of the physical layers, and each layer was assigned a color, such as red for the base or green for the collector. When the designers stacked the two colors over a light source, they produced a third color. This approach provided an efficient way to check whether a part of the geometry was missing or incorrectly drawn. The designers also developed so-called kludge boxes to verify the performance of the design and sometimes for use in production-test equipment (Figure 3).

“Kludge boxes were a necessity in that test equipment did not exist that could measure the performance of the IC,” says Moraveji. “These boxes often used some clever measurement tricks, which would also find their way into the data sheet.” According to Moraveji, the designers used transistor-kit parts in breadboarding a new design idea or to prototype a chip. They performed comprehensive measurements on a breadboard to ensure the validity of a design idea. “Breadboarding was fun, as well as challenging,” he says. “During the process, if a component went bad, it was extremely painful to debug and get it to work again. Technicians, who used to do a neat breadboard, were valuable parts of our team in the development phase.”



Designers used to be able to get into the transistor-level details and even modify the transistor design to create ICs. Today’s designers instead receive standard cells with which to design; they cannot modify them because manufacturing does not support modified designs. In the early days, time to market was less critical than it is now. A 50-transistor circuit—including breadboard design; layout; debugging, which often took place on a probe station; and, typically, some mask changes—would take 18 to 24 months to complete. Now, a period of eight to 10 months is the norm for several-thousand-transistor designs (Figure 4).


Click image to enlarge

The designers used simulation tools for validation but first had to perform manual calculations, and developing breadboards was a standard practice until the mid-’80s. Sometimes, they had to use slide rules to make the paper design work before building the breadboard. They also couldn’t use many library textbooks because they were developing new designs, especially in CMOS. According to Archer, researching articles in various IEEE journals was often more insightful and useful than using textbooks. And, according to Monticelli, recent engineering-school graduates would try to find a good mentor who used blackboards because there were no whiteboards in those days. You learned by reading the latest published papers and meeting other engineers at the watering holes in Silicon Valley. “In many cases, we had to take a multitude of measurements and then use the data to create an explanation [about] the operation of the circuit,” says Dietz.

Moving to plastic-mold compounds caused stress effects that changed low-offset voltages in a chip after the application of the mold. “Sometimes, we would not offer the premium A-grade specs in the plastic package,” explains Maida. “The same part often had two or three electrical grades and two or three temperature grades: commercial, industrial, and military.” He adds that designers always tested military-temperature-range parts over temperature but almost never tested commercial parts in the same way.

According to Dietz, the op amp served as the canary in the coal mine for uncovering any process problems. The sensitive nature of the tight specs in an analog IC provided warnings when the process started going awry. Designers back then had never heard of the phrase “guaranteed by design.” Instead, they “tested the daylights” out of the IC during development. However, Maida claims that this testing was not true for production testing. “Good managers knew what could be put in as a design limit,” he says. “The test-everything mentality came in later, toward the late ’80s, as [part-per-million] quality levels became important.” However, Maida adds, they had to characterize the parts on the bench, which always involved manual measurements and, sometimes, kludge boxes for the tricky measurements, such as settling time, sample-and-hold acquisition time, and linearity.

Fast-forward 40 years, and the customer has hundreds if not thousands of op amps and multiple suppliers to choose from, says Dietz. Once engineers get comfortable with an op amp, they tend to use it over and over again. If they need a little better performance, then the chances are that they can find a product that fits the bill. “It is rare that someone comes to us today and asks for a new op amp,” he says.


Analog-front-end role

Precision op amps are often now parts of the input of integrated analog front ends or integrated into a sensor. Thanks to low output impedance at high frequency, they also drive switched capacitors’ input ADCs and have differential outputs at the corrected common-mode level an ADC requires. According to Moraveji, these amplifiers target use in high-dynamic-range ADC-interface applications with low quiescent power, gigahertz-level gain-bandwidth products, and low input noise.

In these modern amplifiers, besides generic specs, such as open-loop gain, supply current, and input offset voltage, other terms, such as third-order intermodulation, represent distortion and SFDR (spurious-free-dynamic-range) degradation distortion at higher frequencies. High-speed digital variable-gain amplifiers now drive ADCs, usually with serial-bus outputs, to interface painlessly with microcontrollers.

Industrial markets still prefer the old standard of using ±15V power supplies. New process technologies can maintain the ±15V power supplies and provide improved performance, lower power, and programmability, according to Maida. Although some of today’s designers believe that amplifiers that can operate from 1.8V supplies will save power, these devices can instead burn power to achieve performance specs at this supply voltage. One of the first single-cell-powered op amps was the LM10, which the late analog pioneer Bob Widlar designed at National Semiconductor in the ’70s. This single alkaline-cell-powered op amp was stable because many of its transistors operated at nearly the saturation point, Maida explains.

Designers also want their circuits to drive unlimited capacitive loads, and many designers ask for rail-to-rail performance on the input and the output. Most designs do not require this feature, however. Designers must do a thorough analysis of their circuits’ needs to see whether they require rail-to-rail performance to meet the circuits’ specs rather than overspecifying their designs. Nevertheless, according to Maida, no one ever lost a job due to overspecifying an op amp. “Ease of use still sells,” he says.

Designers must push a design to the process limit but not push it over, so they need to clearly understand the boundaries to get a state-of-the-art design. It’s difficult for modern designers to push the limits—often because dice have ever-increasing yield numbers, which are now approximately 90%. IC designers today also must work closely with manufacturing and process teams to achieve the reliable and functional new designs that circuit designers crave. Competent IC designers can work across the boundaries of department functions in modern IC development. They can no longer shoot from the hip because complexities have increased in a process-driven business. Fundamentals remain the same, however, and designers still fight tool issues and push the envelope to get products to customers, says Dietz.

According to Maida, today’s engineers must know everything about what is going into the op amp, as well as everything about the load. Data sheets list a large amount of what a design needs, but, he adds, “Nothing beats a good breadboard to take you to the next level of confidence in the design.”

“Today’s building-block amplifiers are becoming more and more application-specific,” says Monticelli. “There are hundreds—maybe thousands—of product varieties out there from precision to high-speed, but we are seeing more analog front ends, including those that are parts of sensor-interface subsystems. Integration, smaller footprint, and lower power are becoming more prominent today.”

Modern op-amp choices from Texas Instruments have evolved to the point at which many products now tout smaller packages; the availability of single, dual, and quad versions; single-supply, low-power, rail-to-rail performance; and ±18V supplies. Such op amps include the company’s OPA170 family; zero-drift op amps, such as the OPA180 family with integrated electromagnetic-interference filtering; and low-operating-voltage CMOS op amps, such as theOPA314 family and the chopper-stabilized LMP2015 op amp. These devices represent today’s new and creative application- specific architectures and processes.

Bob Dobkin, Linear Technology’s co-founder, vice president of engineering, and chief technology officer, spent his early design days at National Semiconductor, during which he moved op amps beyond the 1-MHz-bandwidth barrier with the LM318 (Figure 5). No fast PNP transistors then existed; there were only lateral NPNs with 1-MHz bandwidth. Improvements in process technology helped, but the greatest speed gains often resulted from clever topological choices. Dobkin employed an architecture that split the input signal into a dc path through the lateral transistors and an ac path with feedforward capacitors that went around the PNP transistors for the 10- to 15-MHz-bandwidth breakthrough. “We were limited to a maximum of eight to 10 mask layers to meet good yields,” Dobkin says.


Click image to view the original schematic

Using too many masks yielded too many defects and, hence, poor yield. The company implemented PCB masks, according to Dobkin—“sometimes with a silk stocking!” New processes now have 20 to 30 mask layers and still get good yields. The availability of masks allowed the development of fully complementary processes using PNP and NPN transistors. Designers can now create amplifiers with hundreds of megahertz of bandwidth because special architectures are no longer necessary for achieving high bandwidth.

Linear Technology’s offerings in the 21st century include the differential-output, low-power, rail-to-rail, high-speed, successive-approximation-register LTC6362 ADC driver; the high-integrationLT6108, which incorporates a precision current-sense amplifier, a voltage reference, and a comparator; and the 500-mA LT1970A power op amp with adjustable precision current limit.

Reference
1. Ihantola, HKJ, and JL Moll, “DesignTheory of a Surface Field-Effect Transistor,” Solid State Electronics, June 1964, pg 423.

You can reach Senior Technical Editor Steve Taranovich at 1-632-413-1834 andsteve.taranovich@ubm.com.



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