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Considerations for CMFB design  

2008-12-02 15:30:32|  分类: IC design |  标签: |举报 |字号 订阅

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1) Enough bandwidth or speed. Must have few parasitic poles to be able to
compensate the common-mode loop without severely limit its bandwidth, or
equivalently its speed. The high speed of the CMFB loop is essential to reject
high-frequency common-mode noise that can otherwise saturate the outputs. It is
critical when designing a CMFB circuit to check the step response (or transient
response) of the CMFB loop.
[Reason for AC CM output component suppression:
If the CM output varies, the DM output swing must be reduced to allow for the
CM output swing.
If two feedback amplifiers are cascaded, any AC CM output voltage from the first
amplifier is a CM input voltage for the second amplifier, and any imbalance in the
second amplifier will convert some of its CM input voltage into a DM output
voltage.]


2) Linearity. The nonlinear interaction between the differential-mode and
common-mode loops results in second and third order harmonic distortions at the
differential output signal.


3) Stability. The stability of the common-mode loop can only be ensured if the
non-dominant pole of the loop is located at higher frequency than the GBW of the
loop.

 

A good on line tutorial for CMFB:

amesp02.tamu.edu/~sanchez/607%20CMFB-FEB2005.pdf

 

 

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